1. Field of the Invention
The present invention relates to a semiconductor die carrier. More particularly, the present invention relates to a semiconductor die carrier with a land grid array of metal pads employed to provide testing and operating signals to a semiconductor die disposed in the semiconductor die carrier.
2. The Background Art
The process of testing programming a semiconductor die to ensure that the circuits formed in the die are operating properly is referred to as Known Good Die. It is known in the art, that bond pads formed on the bare silicon of the semiconductor die may be used to test the semiconductor die during the Known Good Die process, and in the case of a programmable logic device (PLD), to program the semiconductor die during a programming process. PLDs are well known to those of ordinary skill in the art, and typically include uncommitted groups of digital logic, which may be programmed to form higher digital logic functions, and uncommitted routing channels, which may be programmed to connect together the programmed digital logic. An example of a PLD is a field programmable gate array (FPGA). A PLD may be programmed and tested by either the manufacturer of the PLD or by a purchaser of the PLD.
The pitch or distance between the bonds pads on the semiconductor die has tended to decrease as the geometry of the transistors used in the manufacturing process, often complementary metal oxide silicon (CMOS), has been reduced. The migration to smaller processes has been occurring for some time in the semiconductor arts and is expected to continue. One of the problems associated with the decreased pitch between bond pads is that it makes the testing and programming of a semiconductor more difficult. Generally, it has been found that once the bond pad pitch drops below 85 um, testing and programming are no longer very feasible, nor reliable.
One solution to this problem is to package the semiconductor die in a die carrier, test and program the semiconductor die through a land grid array of metal pads disposed on an underside of the die carrier, and then use the die carrier as a typical IC component by attaching or reflowing the die carrier to a printed circuit board (PCB) by the metal pads on the underside of the die carrier. Semiconductor die carriers are well known to those of ordinary skill in the art. They are typically employed to protect the semiconductor die or device from mechanical, thermal and environmental stress. They also provide input and output from the semiconductor device, and are often used in multi-chip modules, wherein a number of carriers or dies are attached to a substrate, such as a PCB, a thick/thin film ceramic, or silicon with an interconnection pattern. Semiconductor die carriers are ubiquitously found in the multi-chip modules that populate consumer, commercial, military and space electronics. They add significantly to the reliability and function of these applications.
FIG. 1 illustrates schematically in cross-section an example of a semiconductor die carrier according to the prior art. The die carrier 10 has a substrate 12 formed from ceramic or other substrate materials well known to those of ordinary skill in the art. Within an opening in the die carrier 10, a semiconductor die 14 is disposed on the substrate 12. On the underside of the substrate 12 is a land grid array of metal pads 16. As is well known in the art, the metal pads 16 are typically arranged in a rectangular array. The number of metal pads 16 and the space in between the metal pads depends on several things, including the size of the semiconductor die and the number of inputs and outputs that are required.
The die carrier 10 may be adhered by the metal pads 16 of the land grid array to a substrate such as a PCB by any of several known methods well known to those of ordinary skill in the art, such as with an epoxy or by growing or attaching a solder ball or column that is then reflowed to the substrate to which the die carrier is being attached. A sealing lid 18 covers the opening in which the semiconductor die 14 is disposed in the substrate 12, and is adhered around the top of the opening by one of several mechanisms well known to those of ordinary skill in the art. The sealing lid 18 protects the semiconductor die from mechanical, thermal and environmental distress.
An electrical connection is made from the semiconductor die 14 by a metal wire 20 to an electrically conductive tab 22 disposed on a tier 24. The electrically conductive tab 22 is coupled to one of the plurality of metal pads 16 in the land grid array by an electrically conductive path 26 in the substrate 12. It should be appreciated that the metal wire 20, the electrically conductive tab 22, and the electrically conductive path 26 represent a plurality of metal wires, a plurality of electrically conductive tabs, and a plurality of electrically conductive paths, respectively.
During the Known Good Die process, the testing of the semiconductor die 14 in the die carrier 10 may need to be performed several times. This may pose a problem, because the metal pads 16 can become damaged during the process. As a consequence, operating signals provided to the semiconductor device 14 during a normal operating mode through the metal pads 16 in the die carrier 10 may be corrupted. This would make the semiconductor device unsuitable for interconnection of to other devices. In the specific case of PLDs, this may be a very significant problem, because PLDs are both programmed and tested, so that the metal pads 16 of the die carrier 10 may be subject to even greater damage.